The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming double gated field effect transistors.
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) Unfortunately, increased device density in CMOS FET can result in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device density is a double gated field effect transistor. Double gated FETs use two gates, one on each side of the body, to facilitate scaling of CMOS dimensions while maintaining an acceptable performance. In particular, the use of the double gate increases the gate area, which allows the transistor to have better current control, without increasing the gate length of the device. As such, the double gated FET is able to have the current control of a larger transistor without requiring the device space of the larger transistor.
Unfortunately, several difficulties arise in the design and fabrication of double gated CMOS transistors. First, the relative dimensions of a double gated transistor are such that it is difficult to reliably fabricate one that has a reliable performance and minimum feature size. Second, the threshold voltage of a double gated transistor is highly dependent upon the material used for the two gates. In particular, current fabrication techniques have generally resulted in a double gated transistor that has either too high a threshold voltage, or too low of a threshold voltage. For example, if the gates are doped the same polarity as the source, the threshold voltage will generally be near or below zero. Conversely, if the gates are doped the opposite polarity of the source, then the threshold voltage will be approximately one volt. Neither result is desirable in most CMOS applications.
Thus, there is a need for improved device structures and methods of fabrications of double gated CMOS devices that provide improved threshold voltage of the resulting double gated CMOS without overly increasing fabrication complexity.